The IC 24LC01/24LC02 uses the I2C addressing proto- col and 2-wire serial interface which includes a bidirec- tional serial data bus synchronized by a clock. Microchip 24LC02 EEPROM are available at Mouser Electronics. Mouser offers inventory, pricing, & datasheets for Microchip 24LC02 EEPROM. Description, Bit/Bit Serial EePROM Write Protect Memory Chips. Company, Pronics. Datasheet, Download 24LC02 datasheet. Quote. Find where to.
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A page write is initiated the same as byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Commerical temperature range 0. Since the device will not acknowledge during a write cycle, this can be used dxtasheet determine when the cycle is complete this feature can be used to maximize bus throughput.
If not, the chip will return to a standby state. For relative timing, refer to timing diagrams. Data Input Setup Time. The microcontroller must terminate the datasheeet write sequence with a stop condition. Stresses exceeding the range specified under “Absolute Maxi. Clock and data transition. Input Capacitance See Note.
Internally organized with 8-bit words, the 1K requires a 7-bit data word address for random word addressing. The device is optimized for use in many industrial and com. Data Input Hold Time.
24kc02 field Part name Part description. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
24LC02 (HOLTEK) PDF技术资料下载 24LC02 供应信息 IC Datasheet 数据表 (4/8 页)
Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. The device address word consist of a mandatory one, zero sequence for the first four most significant bits refer to the diagram show- ing the Device Address.
Internally organized with 8-bit words, the 2K requires an 8-bit data word 24oc02 for random word addressing. A write operation requires an 8-bit data word address following the device address word and acknowledgment.
Serial clock data input. If the device is still busy with the.
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Output Capacitance See Note. The pin is open-drain driven and may be wired-OR with any number of other open-drain or open collector devices. These three bits must compare to their corresponding hard-wired input pins.
Partial page write allowed. After this period the first clock pulse is generated.
These are stress ratings only. The SDA pin is bidirectional for serial data transfer. Upon receipt of this ad- dress, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. A read operation is initi- ated if this bit is daatasheet and a write operation is initiated if catasheet bit is low.
Time in which the bus must be free before a new transmission can start. This happens during the ninth clock cycle.
ACK polling can be initiated immediately. During data transfer, the data line must remain stable whenever the clock line is high. Write operation with built-in timer. After receiving the 8-bit data word, the EEPROM will output a zero and the address- ing device, such as a microcontroller, must datasueet the write sequence with a stop con- dition. Instead, after the EEPROM ac- knowledges the receipt of the first data word, the microcontroller can transmit up to seven more data words.
Output Valid from Clock. Data transfer may be initiated only when the. Characteristics 2lc02 Description Timing Diagrams. Hardware controlled write protection. The higher data word address bits are not incremented, re- taining the memory page row location refer to Page write timing.